A single-channel design refers to a synchronous digital design that processes a continuous stream of data all of the same channel. For example, the design may receive a word of data in each clock cycle, with the exception of “disabled” cycles which are cycles in which the design receives no data. Architect circuits that process independent data streams from multiple channels typically use a single, common register transfer level (RTL) core design with modifications from a corresponding single-channel design.
A time-sliced logic design is often used to process data from multiple channels, where a subset of the processing cycles is assigned to each channel. Internally a common design core is shared by all channels, which keeps switching state every time a new channel's data comes in, which can happen as often as once per clock cycle for example.
A conventional time-sliced logic design is usually cycle-based, which statically allocates a specific, repeated subset of an N-cycle period to each channel. For example, the logic may be capable of switching from channel X to channel Y at each clock cycle; sometimes X will be the same as Y.
For example, a cycle-based time-sliced logic that receives data for channel X at cycle C at its input, can produce data for channel X at its output at cycle (C+M), where M is a constant and for the rest of this description, e.g., M=1. The produced data will be a processed version of the data that was received for channel X at cycle (C−L), where L is the latency of the original single-channel design. In that sense, the cycle-based time-sliced design can preserve the latency of the single-channel design.
For example assume a 3-channel time-sliced design whose channels are allocated with bandwidths equal to 48%, 24%, 22% of the total bandwidth respectively, with 6% of the maximum potential bandwidth remaining unused. Out of every N=4 clock, this logic can allocate 2 cycles to the 1st channel and 1 cycle to each of the other two channels. In a total of 100(=25×4) cycle periods, channel #1 gets a total of two disabled cycles, channel #2 gets one disabled cycle and channel #3 gets three disabled cycles. The disabled cycles can appear anywhere in the 100-cycle period. In order to switch from channel X to channel Y, the logic needs to save the current value of each register (its “state”) for channel X in some internal memory, and load the last saved state of channel Y. In other words, the logic needs to perform a context switch to switch channel. The state includes the values of all registers in the logic, and has to be maintained in some form of internal memory, which can potentially become quite large. Unfortunately, this implies that the logic needs to include enough memory to simultaneously hold the states of all channels that it processes. The demand for a large memory often makes it counter-productive to timeslice a design, especially if the number of channels is low, e.g., less than 4. In that case, it would be often more area efficient to simply replicate the design N times, once for each channel. Therefore, it would be advantageous to reduce or eliminate the need for saving and reloading the states during context switching.